📚 R-S (Reset-Set) Flip-Flop
Introduction
An R-S Flip-Flop (also called SR Flip-Flop) is the simplest type of flip-flop.
It is a basic memory element that stores one bit of information — either 0 or 1 — based on two inputs:
- S = Set
- R = Reset
✅ Purpose:
- Set means “make the output 1”.
- Reset means “make the output 0”.
It operates on a clock signal and is edge-triggered (changes happen only when a clock edge occurs).
🔥 Construction of R-S Flip-Flop
There are two common ways to construct an R-S Flip-Flop:
1. Using NAND gates
2. Using NOR gates
R-S Flip-Flop using NOR Gates
The basic circuit looks like this:
+-----+ +-----+
R -| | | |- Q
| NOR |-------| NOR |
S -| | | |- Q'
+-----+ +-----+
- The output of each NOR gate is connected back to the input of the other.
- Feedback loop allows memory storage.
🌟 Operation of R-S Flip-Flop
| S (Set) | R (Reset) | Next State (Q) | Description |
|---|---|---|---|
| 0 | 0 | No Change | Memory (hold last) |
| 0 | 1 | 0 | Reset (output = 0) |
| 1 | 0 | 1 | Set (output = 1) |
| 1 | 1 | Invalid | Forbidden state |
✅ Explanation:
- S = 1, R = 0 → Set the flip-flop: Output Q = 1.
- S = 0, R = 1 → Reset the flip-flop: Output Q = 0.
- S = 0, R = 0 → Hold the previous state (no change).
- S = 1, R = 1 → Invalid condition: Both Set and Reset are 1, which leads to unpredictable output (should be avoided).
🧠 Truth Table of R-S Flip-Flop
| Clock Edge | S | R | Q (Next State) | Operation |
|---|---|---|---|---|
| Rising/Falling | 0 | 0 | No change | Memory |
| Rising/Falling | 0 | 1 | 0 | Reset |
| Rising/Falling | 1 | 0 | 1 | Set |
| Rising/Falling | 1 | 1 | Invalid | Not allowed |
⏰ Working with Clock
Clock signal is often connected to enable or control when the flip-flop responds.
- Edge-Triggered: Flip-flop reacts only on rising (↑) or falling (↓) edge.
- Level-Sensitive (in some designs): Flip-flop reacts during a high/low level of clock.
Usually, positive edge triggering is preferred (change on rising edge).
✅ Symbol for edge-triggered RS Flip-Flop:
+-----+
S --| |
R --| RS |--> Q
Clk-|> |
+-----+
(▲ = rising edge trigger)
⚡ Timing Diagram
A timing diagram shows how input signals (S and R) and the output (Q) behave over time.
📈 Important points:
- When S is triggered high with clock pulse, Q becomes 1.
- When R is triggered high with clock pulse, Q becomes 0.
- If both are low, Q remains the same.
- If both are high, it leads to invalid (confused) output.
(Would you like me to prepare a neat sample timing diagram too?)
⚙️ Applications of R-S Flip-Flop
- Memory circuits (single-bit storage).
- Control units for setting and resetting flags.
- Simple latch circuits (locking systems).
- Debounce circuits (removing mechanical switch noise).
- Alarm systems, where setting and resetting states are important.
🚨 Problem with R-S Flip-Flop
The major problem with the basic R-S flip-flop is the invalid condition:
- When S = 1 and R = 1 at the same time, outputs become unpredictable.
- This can cause glitches and errors in digital circuits.
- 🛠️ Solution: JK Flip-Flop or D Flip-Flop were invented to fix this problem.
📋 Quick Summary
| Feature | Description |
|---|---|
| Type | Sequential Circuit (Flip-Flop) |
| Inputs | Set (S), Reset (R) |
| Outputs | Q (normal), Q’ (complement) |
| Triggering | Edge-sensitive (Clock-based) |
| Main Issue | Invalid state when S=1 and R=1 |
| Usage | Memory, Control, Latch systems |
✨ Conclusion
The R-S Flip-Flop is the foundation of memory elements in computers and electronics.
While simple, it introduces students to important concepts like sequential logic, memory storage, and the necessity of careful control of input signals.
It also motivates the invention of more sophisticated flip-flops like JK and D Flip-Flops to improve circuit reliability.